Jump to content

Hardware-Architekturen für maschinelles Lernen in eingebetteten und verteilten Systemen

Fast facts

Content

The development of specialized hardware accelerators for machine learning is an important key technology, especially for the development of intelligent mobile systems. This article compares different hardware architectures with regard to their properties for machine learning and provides an outlook on the development of a heterogeneous ASIC based on open source technologies, consisting of a RISC-V CPU and an application-specific IP core for machine learning, which is particularly optimized for energy efficiency.

Notes and references

This site uses cookies to ensure the functionality of the website and to collect statistical data. You can object to the statistical collection via the data protection settings (opt-out).

Settings(Opens in a new tab)